¡¡

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LSI Families of ICs

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Counter ICs - Ä«¿îÅÍ

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Decade

- ½ÊÁø Ä«¿îÆ®

 

 

Binary

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Multi-Mode - ´ÙÁß ¸ðµå

 

 

 

 

 

 

Divider ICs - ºÐÁÖ±â

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50Hz/60Hz Line Frequency - ¶óÀÎÁÖÆļö ¼±ÅÃ

 

 

Selectable Six Decade - ¼±Åà °¡´É 6 µðÄÉÀ̵å

 

 

 

 

 

 

Incremental Encoder Interface ICs - ÀÎÅ©¸®¸àƲ ¿£ÄÚ´õ

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Quadrature Decoders - 4 »ó µðÄÚ´õ

 

 

Quadrature Counters - 4 »ó Ä«¿îÅÍ

 

 

 

 

 

 

Lighting Control ICs - Á¶¸íÁ¦¾î 

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Motion Detector with Triac Interface

 

 

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Motion Detector with Latching Relay Interface

 

 

 

 

 

 

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Light Activated Timer

 

 

SE-QCNTR-A Ä«¿îÅÍ

A/B »ó ¶Ç´Â Pulse/Dir ½ÅÈ£ ÀÔ·Â
ÃÖ´ë 2.5MHz A/B »ó ÁÖÆļö Ä«¿îÆ®

ÁøÇà¹æÇâ(+/-) , ¼Ò¼öÁ¡ À§Ä¡, 4 x Äõ´õ·¡ÃÄ ¸ðµå 
 µð½ºÇÁ·¹ÀÌ À¯´ÏÆ® (X1, X2, X5, X10) ±â´ÉÀ» ¼³Á¤ °¡´ÉÇÕ´Ï´Ù.
RS-422 Ãâ·ÂÇü, TTL Ãâ·ÂÇü  ¿£ÄÚ´õ »ç¿ë °¡´ÉÇÕ´Ï´Ù. 
LSI/CSI »çÀÇ °í¼Ó Ä«¿îÅÍ LS7366R À» »ç¿ëÇÏ¿´½À´Ï´Ù. 

DC 5V ·Î µ¿ÀÛÇϸç A/B/Index ½ÅÈ£´Â RS-422, TTL ·¹º§ ¶Ç´Â 5V CMOS ·¹º§ ÀÔ´Ï´Ù.

¡¡

http://www.robot.kr/se-qcntr-a/index.htm

¡¡

¡¡

¡¡Linear / Rotary Encoder A B »ó Ä«¿îÅÍ IC


Quadrature ½ÅÈ£ ü¹è
LS7183 - Quadrature Clock Converter (Up Clock, Down Clock)
¿£ÄÚ´õ AB »ó½ÅÈ£·ê UP, Down Ŭ·ÏÀ¸·Î º¯È¯ÇÕ´Ï´Ù. ¿À½Ç·¹ÀÌÅÍ°¡ ³»ÀåµÇ¾î ÀÖÀ¸¸ç Ãâ·Â ÆÞ½ºÆøÀ» ¹ÙÀ̾ ÀúÇ×°ª¿¡ ÀÇÇÏ¿© °áÁ¤ÇÒ ¼ö ÀÖ½À´Ï´Ù.
SN74190, SN74193, CD40193 ¿¡ Á÷°áÇÏ¿© »ç¿ëÇÒ ¼ö ÀÖ½À´Ï´Ù.

* Up Ŭ·Ï / Down Ŭ·Ï
* Ãâ·ÂÆÞ½ºÆøÀ» 200nS~400nS ¼³Á¤
* 1X, 2X, 4X ü¹è
* TTL, CMOS ȣȯ Ãâ·Â
* 3V ~ 5.5V µ¿ÀÛÀü¾Ð

LS70183: 8 Pin DIP
LS70183-S: 8 Pin SOP

LS7184 - Quadrature Clock Converter (Clock, Up/Down ¹æÇâ)
¿£ÄÚ´õ AB »ó½ÅÈ£¸¦ CLOCK ½ÅÈ£¿Í UP/Down ¹æÇâ½ÅÈ£·Î ºÐÇØÇÕ´Ï´Ù. ¿À½Ç·¹ÀÌÅÍ È¸·Î¸¦ ³»ÀåÇÏ°í ÀÖÀ¸¸ç Ŭ·Ï ÆÞ½ºÆøÀº ¹ÙÀ̾ ÀúÇ׿¡ ÀÇÇÏ¿© º¯È­ÇÒ¼ö ÀÖ½À´Ï´Ù.
CD4516 ¿¡ Á÷°áÇÏ¿© »ç¿ëÇÒ ¼ö ÀÖ½À´Ï´Ù.
* Up Ŭ·Ï / Down Ŭ·Ï
* Ãâ·ÂÆÞ½ºÆøÀ» 200nS~400nS ¼³Á¤
* 1X, 2X, 4X ü¹è
* TTL, CMOS ȣȯ Ãâ·Â
* 3V ~ 5.5V µ¿ÀÛÀü¾Ð

LS70183: 8 Pin DIP
LS70183-S: 8 Pin SOP

A/B »ó ¿£ÄÚ´õ Ä«¿îÅÍ
LS7166 - 24 Bit Quadrature Counter
24 ºñÆ® ¸ÖƼ¸ðµå Ä«¿îÅÍ ÀÔ´Ï´Ù. ÇÁ·Î±×·¥¿¡ ÀÇÇÏ¿© ¿©·¯ °¡ÁöÀÇ Ä«¿îÅÍ ¸ðµå¸¦ ¼³Á¤ÇÕ´Ï´Ù. ¿ÜºÎ Ŭ·ÏÀÌ ÇÊ¿äÄ¡ ¾ÊÀ¸¸ç °í¼Ó Ä«¿îÆ®°¡ °¡´ÉÇÕ´Ï´Ù. ±¹³»ÀÇ À¯¸í3 Â÷¿ø ÃøÁ¤±â(CMM)¿Í ¹æÀü °¡°ø±â(EDM)ÀÇ ¸®´Ï¾î ½ºÄÉÀÏ Ä«¿îÅÍ·Î ¿À·¨µ¿¾È »ç¿ëµÈ »ê¾÷ Ç¥ÁØ IC ÀÔ´Ï´Ù.
8 ºñÆ® µ¥ÀÌÅ͹ö½º ¹æ½ÄÀÇ ÇÁ·Î¼¼¼­¿Í ¿¬°áÇÏ¿© »ç¿ëÇÕ´Ï´Ù. 
* 8 Bit µ¥ÀÌÅÍ ¹ö½º
* ÇÁ·Î±×·¥¿¡ ÀÇÇÑ ¸ÖƼ¸ðµå¼³Á¤:
1x, 2x, 4x Qudrature Counter
Up/Down, Binary, BCD, 24Hour Clock.
Divide-by-N
* DC ¿¡¼­ 25MHz ±îÁö Ä«¿îÆ® °¡´É
* 24-Bit ºñ±³±â·Î ÇÁ¸®¼Â °ª°ú ºñ±³
* »óÅ·¹Áö½ºÆ® Àб⠰¡´É
* CMOS/TTL ÀÔÃâ·Â ȣȯ
* 3V ºÎÅÍ 5.5V ±îÁö µ¿ÀÛ

LS7166: DIP
LS7166-S: SOIC
LS7166-TS24: 24Pin TSSOP

LS7266R1 - 24Bit 2Axis Quadrature Counter
1°³ÀÇ ÆÐÅ°Áö¿¡ µ¶¸³ÀûÀÎ 24ºñÆ® Ä«¿îÅÍ 2 °³¸¦ ³»ÀåÇÏ°í ÀÖ½À´Ï´Ù. Quadrature ÀԷ¿¡ µðÁöÅÐ ÇÊÅ͸¦ ³»ÀåÇÏ¿© ³ëÀÌÁî¿¡ °­·ÂÇÑ ½Ã½ºÅÛ ¼³°è°¡ °¡´ÉÇÕ´Ï´Ù. Quadrature ¸ðµå¿¡¼­ 17MHz(ÃÖ´ë)ÀÇ Å¬·ÏÀÌ ÇÊ¿äÇϸç À̶§ 2.2MHz ÀÇ Quadrature ÁÖÆļö±îÁö Ä«¿îÆ® °¡´ÉÇÕ´Ï´Ù.
8 ºñÆ® µ¥ÀÌÅ͹ö½º ¹æ½ÄÀÇ ÇÁ·Î¼¼¼­¿Í ¿¬°áÇÏ¿© »ç¿ëÇÕ´Ï´Ù. 
* 30MHz Ä«¿îÆ® ÁÖÆļö 
* 4.3MHz 4x A/B »ó Ä«¿îÆ®
* ¿ÏÀü µ¶¸³µÈ µÎ°³ÀÇ 24Bit Ä«¿îÅÍ
* A/B ÀÔ·Â µðÁöÅÐ ÇÊÅ͸µ
* ÇÊÅÍ¿µ¿ª ÃÊ°ú ½ÅÈ£´Â Error Flag ¹ß»ý
* x1, x2, x4 Quadrature Ä«¿îÅÍ ¸ðµå

LS7266R1: 28 Pin DIP
LS7266R1-SD: Skinny DIP
LS7266R1-S: SOIC
LS7266R1-TS: TSSOP

LS7366R - 32 Bit Quadrature Counter with Serial Interface
¼­ºê¹ÌÅ©·Ð ÀÌÇÏ Á¤µµÀÇ ·¹ÀÌÁ® ½ºÄÉÀÏ°ú °°Àº ÃÊÁ¤¹Ð, ÃÊ°í¼Ó¿ë Quadrature Ä«¿îÅÍ ÀÔ´Ï´Ù. 9.6MHz ÀÇ Quadrature ½ÅÈ£¸¦ Ä«¿îÆ® ÇÒ ¼ö ÀÖ½À´Ï´Ù. (5V, 40MHz FCKI) Index ½ÅÈ£¿¡ ÀÇÇÏ¿© Ä«¿îÅÍ µ¥ÀÌÅÍ°ªÀÇ ÇÁ¸®¼ÂÀÌ °¡´ÉÇÕ´Ï´Ù. (¸¶ÀÌÅ©·ÎÇÁ·Î¼¼¼­ÀÇ ÀÎÅÍ·´Æ® ±â´ÉÀ» »ç¿ëÇÏÁö ¾ÊÀ½)
SPI ÀÎÅÍÆäÀ̽º¸¦ °¡Áø ¸¶ÀÌÅ©·Î ÇÁ·Î¼¼¼­¿¡ ¿¬°áÇÏ¿© »ç¿ëÇÕ´Ï´Ù.
* 1x, 2x, 4x Quadrature Counter
* 32 ºñÆ® µ¥ÀÌÅÍ·¹Áö½ºÅÍ, ºñ±³·¹Áö½ºÅÍ
* 32 ºñÆ® Ãâ·Â·¹Áö½ºÅÍ
* Index ÆÞ½º¿¡ ÀÇÇÑ Ä«¿îÅͷεå(ÇÁ¸®¼Â)
* 8 ºñÆ®, 16ºñÆ®, 24ºñÆ®, 32 ºñÆ® µ¿ÀÛ¸ðµå 

LS7366R: DIP
LS7366R-S: SOIC
LS7366R-TS: TSSOP

SPI/MICRPWIRE
MOSI, MISO, SS/, SCK

¡¡

LS7366¿¡´Â Ç¥ÁØÇüÀÇ 10MHz Å©¸®½ºÅаú 33 pF ÀÇ ·Îµå ijÆнÃÅ͸¦ »ç¿ëÇÕ´Ï´Ù.

LS7366¿¡ Å©¸®½ºÅÐ »ç¿ë ½Ã 12MHz ÀÌÇÏ ÁÖÆļö¸¦ »ç¿ëÇÏ¿©¾ß ÇÕ´Ï´Ù. ³ôÀº ÁÖÆļöÀÇ Å©¸®½ºÅÐÀº ¹ßÁøÇÏÁö ¾Ê½À´Ï´Ù. ¶ÇÇÑ ATS ÇüÀº ÁÖÆļö¿¡ °ü°è¾øÀÌ ¹ßÁøÇÏÁö ¾ÊÀ¸¹Ç·Î »ç¿ëÇÏÁö ¾Ê¾Æ¾ß ÇÕ´Ï´Ù. ³ôÀº ÁÖÆļö¸¦ ¿øÇϸé (5V ¿¡¼­ 40MHx) ¿À½Ç·¹ÀÌÅ͸¦ »ç¿ëÇϰųª CPU Ŭ·°À» »ç¿ëÇϽñ⠹ٶø´Ï´Ù.


LS7366R À» ATmega128 º¸µå¿¡ ¿¬°áÇÕ´Ï´Ù.
 ÇÁ·Î±×·¥ ´Ù¿î·Î´õ´Â AVRISP-MK2 ¸¦ »ç¿ëÇÏ¿© PC ¿Í ¿¬°áÇÕ´Ï´Ù.


LS7366R ÀÇ Å©¸®½ºÅÐ ¿¬°á


4 °³ ¹ÙÀÌÆ®¸¦ PORT ¿¡ Á÷Á¢ Ãâ·ÂÇÏ¿© LED ·Î È®ÀÎÇÕ´Ï´Ù.


Å×½ºÆ®¿¡ »ç¿ëÇÑ Grayhill A,B»ó 256 ÆÞ½º ¿£ÄÚ´õ

LS7366R ÀÀ¿ë¿¹ ( C ¼Ò½º ÇÁ·Î±×·¥ °ø°³)

LS7366R À» ATMEGA128 ¿¡ ¿¬°á(SPI)ÇÑ ¿¹ÀÔ´Ï´Ù. 4 ¹ÙÀÌÆ®ÀÇ Ä«¿îÆ® °ªÀ» Àоî PORTF, PORTA, PORTC, PORTD ¿¡ µð½ºÇÁ·¹ÀÌ ÇÕ´Ï´Ù.

ÇÁ·Î±×·¥ ¼ø¼­ÀÔ´Ï´Ù.

(1) ATMega128 ÀÇ ÃʱâÈ­: LED¸¦ Á¡µîÇϱâ À§ÇÑ PORT¿Í SPI°ü·Ã Æ÷Æ®¸¦ ÃʱâÈ­ ÇÕ´Ï´Ù. 4 ¹ÙÀÌÆ®ÀÇ Ä«¿îÅÍ °ªÀ» LED ·Î Á¡µîÇϵµ·Ï PORTF, PORTA, PORTC, PORTD ¸¦ Ãâ·ÂÀ¸·Î ¼³Á¤ÇÕ´Ï´Ù.

DDRF = 0xFF;        // Atmega128 ÀÇ PortF ¸¦ Ãâ·ÂÆ÷Æ®·Î ÁöÁ¤ 31 - 24 (MSB)
DDRA = 0xFF;       // Atmega128 ÀÇ PortA ¸¦ Ãâ·ÂÆ÷Æ®·Î ÁöÁ¤ 23 - 16
DDRC = 0xFF;       // Atmega128 ÀÇ PortC ¸¦ Ãâ·ÂÆ÷Æ®·Î ÁöÁ¤ 15 - 08
DDRD = 0xFF;       // Atmega128 ÀÇ PortD ¸¦ Ãâ·ÂÆ÷Æ®·Î ÁöÁ¤ 07 - 00 (LSB)


(2) SPI ÃʱâÈ­: ATmega128 ¿¡¼­ SPI ¸¦ »ç¿ëÇÏ´Â °ÍÀ¸·Î ¼³Á¤ÇÏ¿©µµ SPI °ü·Ã Æ÷Æ®±îÁö ÀÚµ¿ ¼³Á¤µÇÁö ¾ÊÀ¾´Ï´Ù. SPI ÀÇ SS, SCK, MOSI ´Â Ãâ·ÂÀ¸·Î MISO ´Â ÀÔ·ÂÀ¸·Î ¹æÇâ ¼³Á¤ÇÕ´Ï´Ù. 

DDRB = 0x07;      // Atmega128 ÀÇ PORTB.0 (SS), PORTB.1(SCK), PORTB.2(MOSI)¸¦ 
                         // Ãâ·ÂºñÆ®·Î PORTB.3(MISO)¸¦ ÀÔ·Â ºñÆ®·Î ¼³Á¤ÇÕ´Ï´Ù.

ATmega128 ÀÇ SPI ·¹Áö½ºÅ͸¦ ÃʱâÈ­ ÇÕ´Ï´Ù.

SPCR = 0x53;    // SPE¿Í MSTR ºñÆ®¸¦ 1 ·ÎÇÏ°í SPR1, SPR0 ¸¦ 1 ·Î ÇÏ¿© 
                       // SCK ÁÖÆļö¸¦ fOSC/64 ·Î ¼³Á¤ÇÕ´Ï´Ù. 
                       // SCK ¼Óµµ´Â ½ÇÇèÀ» Çϱâ À§ÇÏ¿© ³·°Ô ÇÏ¿´½À´Ï´Ù.
SPSR = 0x00;    // SPI2X ¸¦ 0 À¸·Î ÇÕ´Ï´Ù. (º¸Åë ¼Óµµ)

(3) LS7366R ÀÇ ÃʱâÈ­: 
MDR0°ú MDR1ÀÇ ÃʱâÈ­´Â °¢°¢ 2 ¹ÙÀÌÆ®¸¦ LS7366R ·Î Àü¼ÛÇÕ´Ï´Ù.

SS¸¦ High ¿¡¼­ Low
0x88 À» LS7366R·Î Àü¼Û (MDR0 ·¹Áö½ºÅÍ, WR ¸ðµå) 
0x03 À» LS7366R·Î Àü¼Û (x4 Ä«¿îÆ® ¸ðµå ¼³Á¤)
SS¸¦ Low ¿¡¼­ High 

SS¸¦ High ¿¡¼­ Low
0x90 À» LS7366R·Î Àü¼Û (MDR1 ·¹Áö½ºÅÍ, WR ¸ðµå) 
0x00 À» LS7366R·Î Àü¼Û (4 Byte Ä«¿îÆ® ¸ðµå, Ä«¿îÅÍ Enable ¸ðµå ¼³Á¤)
SS¸¦ Low ¿¡¼­ High 

(4) LS7366R ÀÇ CNTR ·¹Áö½ºÅ͸¦ 0À¸·Î ¸®¼ÂÆ® ÇÕ´Ï´Ù. (¼±Åûç¾ç)

SS¸¦ High ¿¡¼­ Low
0x20 À» LS7366R·Î Àü¼Û (CNTR ·¹Áö½ºÅÍ, CLR ¸ðµå)
SS¸¦ Low ¿¡¼­ High 

LS7366R·Î ºÎÅÍ µ¥ÀÌÅÍ°ªÀ» ÀнÀ´Ï´Ù. AB »ó ½ÅÈ£¿¡ µû¶ó Ä«¿îÆ® µÇ´Â ·¹Áö½ºÅÍ´Â CNTR ·¹Áö½ºÅÍ ÀÔ´Ï´Ù. CNTR ·¹Áö½ºÅÍÀÇ °ªÀº CNTR ·¹Áö½ºÅ͸¦ Á÷Á¢ Àд°ÍÀº ¾Æ´Ï°í OTR·¹Áö½ºÅÍ·Î º¹»ç (4 ¹ÙÀÌÆ® µ¿½Ã ·¡Ä¡)ÇÑÈÄ OTR ·¹Áö½ºÅ͸¦ ÀнÀ´Ï´Ù.

(5) LS7366RÀÇ CNTR ·¹Áö½ºÅÍ°ªÀ» OTR ·Î º¹»ç(·¡Ä¡)ÇÕ´Ï´Ù. 1 ¹ÙÀÌÆ® ¸¦ Àü¼ÛÇÕ´Ï´Ù.

SS¸¦ High ¿¡¼­ Low
0xE8À» LS7366R·Î Àü¼Û
SS¸¦ Low ¿¡¼­ High 

(6) OTR ·¹Áö½ºÅÍ Àб⠸í·ÉÀ¸·Î 1 ¹ÙÀÌÆ®¸¦ Àü¼ÛÇÏ°í 4 Byte ÀÇ OTR ·¹Áö½ºÅ͸¦ ÀнÀ´Ï´Ù.

SS¸¦ High ¿¡¼­ Low
0x68 À» LS7366R·Î Àü¼Û
0x00À» LS7366R·Î Àü¼ÛÇÏ°í SPDR (ATmega128 ÀÇ SPIµ¥ÀÌÅÍ)°ªÀ» Àоî PORTF ¿¡ Ãâ·Â
0x00À» LS7366R·Î Àü¼ÛÇÏ°í SPDR (ATmega128 ÀÇ SPIµ¥ÀÌÅÍ)°ªÀ» Àоî PORTA ¿¡ Ãâ·Â
0x00À» LS7366R·Î Àü¼ÛÇÏ°í SPDR (ATmega128 ÀÇ SPIµ¥ÀÌÅÍ)°ªÀ» Àоî PORTC ¿¡ Ãâ·Â
0x00À» LS7366R·Î Àü¼ÛÇÏ°í SPDR (ATmega128 ÀÇ SPIµ¥ÀÌÅÍ)°ªÀ» Àоî PORTD ¿¡ Ãâ·Â
SS¸¦ Low ¿¡¼­ High 

* SPI ¿¡¼­´Â µ¥ÀÌÅ͸¦ Àбâ À§ÇÏ¿© ¾î¶°ÇÑ µ¥ÀÌÅÍ(¿©±â¼­ 0x00 À̸ç LS7366R¿¡¼­ ¼ö½Å µÇÁö¸¸ ¾Æ¹«·± Àǹ̴ ¾ø½À´Ï´Ù.)¸¦ SPI ·Î º¸³»¾ß LS7366R·Î ºÎÅÍ µ¥ÀÌÅ͸¦ ÀÐÀ» ¼ö ÀÖ½À´Ï´Ù.

(7) ¿¬¼ÓÇؼ­ Àд °æ¿ì (5),(6)ÀÇ °úÁ¤À» ¹Ýº¹ÇÕ´Ï´Ù.

¡¡

¿¹Á¦ÇÁ·Î±×·¥Àº Imagecraft »çÀÇ ICC-AVR µ¥¸ð¹öÁ¯À» ÀÌ¿ëÇÏ¿´½À´Ï´Ù.

¼Ò½ºÇÁ·Î±×·¥ ´Ù¿î·Îµå (ICC-AVR C ÄÄÆÄÀÏ·¯¸¦ ´Ù¿î¹Þ°í ¾ÐÃà ÇØÁöÇÑ Æú´õ¿¡¼­ Menu-> project ¿ÀÇÂÇÏ¸é µË´Ï´Ù.)

SE-ATMEGA-M º¸µå¿¡¼­ µ¿ÀÛÇϵµ·Ï ÀÛ¼ºµÇ¾ú½À´Ï´Ù.

Imagecraft ICC AVR V7 µ¥¸ð¹öÁ¯ ´Ù¿î·Îµå

//ICC-AVR application builder : 2009-08-04 ¿ÀÈÄ 11:03:25
// Target : M128
// Crystal: 4.000Mhz
// Fuse: E-FF H-D9 L-E3
//
// Programmed by Junghoon Kim
//
#include <iom128v.h>
#include <macros.h>
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// IR. The IR is an 8-bit register that fetches instruction bytes from B2 B1 B0 = XXX (Don't care)
// the received data stream and executes them to perform such B5 B4 B3 = 000: Select none
// functions as setting up the operating mode for the chip (load the = 001: Select MDR0
// MDR) and data transfer among the various registers. = 010: Select MDR1
// = 011: Select DTR
// = 100: Select CNTR
// +----+----+----+----+----+----+----+----+ = 101: Select OTR
// | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 | = 110: Select STR
// +----+----+----+----+----+----+----+----+ = 111: Select none
// B7 B6 = 00: CLR register
// = 01: RD register
// = 10: WR register
// = 11: LOAD register
#define SELECT_MDR0 0b00001000 // Select MDR0
#define SELECT_MDR1 0b00010000 // Select MDR1
#define SELECT_DTR 0b00011000 // Select DTR
#define SELECT_CNTR 0b00100000 // Select CNTR
#define SELECT_OTR 0b00101000 // Select OTR
#define SELECT_STR 0b00110000 // Select STR

#define CLR_REG 0b00000000 // CLR register
#define RD_REG 0b01000000 // RD register
#define WR_REG 0b10000000 // WR register
#define LOAD_REG 0b11000000 // LOAD register
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// MDR0. The MDR0 (Mode Register 0) is an 8-bit rean/write register that sets up the operating mode for LS7366R. The MDR0 is
// written into by executing the "write-to-MDR0" instruction via the instruction register. Upon power up MDR0 is cleared to zero. The
// following is a breakdown of the MDR bits:
//
//
// +----+----+----+----+----+----+----+----+
// | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
// +----+----+----+----+----+----+----+----+
//
// B1 B0 = 00: non-quadrature count mode. (A = clock, B = direction).
// = 01: x1 quadrarure count mode (one count per quadrature cycle).
// = 10: x2 quadrature count mode (two counts per quadrature cycle).
// = 11: x4 quadrature count mode (four counts per quadrature cycle).
// B3 B2 = 00: free-running count mode.
// = 01: single-cycle count mode (counter disabled with carry borrow, re-enabled with reset or load).
// = 10: range-limit count mode (up and down count-ranges are limited between DTR and zero,
// respectively; counting freezes at these limits but resumes when direction reverse).
// = 11: modulo-n count mode (input count clock frequency is divided by a factor of (n+1).
// B5 B4 = 00: disable index
// = 01: configure index as the "load CNTR"input (transfer DTR to CNTR).
// = 10: configure index as the "reset CNTR" input (clears CNTR to 0).
// = 11: configure index as the "load OTR"input(transfer CNTR to OTR).
//
// B6 = 0: Asynchronous index
// = 1: Synchoronous Index (oerridden in non-quadrature mode)
// B7 = 0: Filter clock division factor = 1
// = 1: Filter clock division factor = 2
//
#define NON_QUAD 0b00000000 // non-quadrature counter mode.
#define X1_QUAD 0b00000001 // x1 quadrature counter mode.
#define X2_QUAD 0b00000010 // x2 quadrature counter mode.
#define X4_QUAD 0b00000011 // x4 quadrature counter mode.
#define FREE_RUN 0b00000000 // free-running count mode.
#define SINGLE_CYCLE 0b00000100 // single-cycle count mode.
#define RANGE_LIMIT 0b00001000 // range-limit count mode.
#define MODULO_N 0b00001100 // modulo-n count mode.
#define DISABLE_INDEX 0b00000000 // disable index.
#define INDEX_AS_LOAD_CNTR 0b00010000 // configure index as the "load CNTR" input(clears CNTR to 0).
#define INDEX_AS_RESET_CNTR 0b00100000 // configure index as the "reset CNTR" input(clears CNTR to 0).
#define INDEX_AS_LOAD_OTR 0b00110000 // configure index as the "load OTR" input(transfer CNTR to OTR).
#define ASYCHRONOUS_INDEX 0b00000000 // Asynchronous index
#define SYNCHRONOUS_INDEX 0b01000000 // Synchoronous index
#define FILTER_CDF_1 0b00000000 // Filter clock division factor = 1
#define FILTER_CDF_2 0b10000000 // Filter clock division factor = 2
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// MDR1. The MDR1 (Mode Register 1) is an 8-bit read/write register which is appended to MDR0 for additional modes.
// Upon power-up MDR1 is cleared to zero
//
// +----+----+----+----+----+----+----+----+
// | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
// +----+----+----+----+----+----+----+----+
//
// B1 B0 = 00: 4-byte counter mode
// = 01: 3-byte counter mode
// = 10: 2-byte counter mode
// B2 = 0: Enable counting
// = 1: Disable conting
// B3 = : not used
// B4 = 0: NOP
// = 1: FLAG on IDX (B4 of STR) -----+
// B5 = 0: NOP |
// = 1: FLAG on CMP (B5 of STR) | NOTE: Applicable to both
// B6 = 0: NOP | LFLAG/and DFLAG
// = 1: FLAG on BW (B6 of STR) |
// B7 = 0: NOP |
// = 1: FLAG on CY (B7 of STR) -----+
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
#define FOUR_BYTE_COUNT_MODE 0b00000000 // 4-byte counter mode
#define THREE_BYTE_COUNT_MODE 0b00000001 // 3-byte counter mode
#define TWO_BYTE_COUNT_MODE 0b00000010 // 2-byte counter mode
#define ENABLE_COUNTING 0b00000000 // Enable counting
#define DISABLE_COUNTING 0b00000100 // Disable counting
#define FLAG_ON_IDX 0b00010000 // FLAG on IDX (B4 of STR)
#define FLAG_ON_CMP 0b00100000 // FLAG on CMP (B5 of STR)
#define FLAG_ON_BW 0b01000000 // FLAG on BW (B6 of STR)
#define FLAG_ON_CY 0b10000000 // FLAG on CY (B7 of STR)
//////////////////////////////////////////////////////////////////////////////////////////////////////////////

#define LS7366_SS_H_L PORTB &= 0b11111110; // Device Select or Start
#define LS7366_SS_L_H PORTB |= 0b00000001; // Device Unselect or End

//////////////////////////////////////////////////////////////////////////////////////////////////////////////
void port_init(void)
{
PORTA = 0xFF;
DDRA = 0xFF;
PORTB = 0x07;
DDRB = 0x07;
PORTC = 0xFF;
//m103 output only
DDRC = 0xFF;
PORTD = 0xFF;
DDRD = 0xFF;
PORTE = 0x00;
DDRE = 0x00;
PORTF = 0xFF;
DDRF = 0xFF;
PORTG = 0x00;
DDRG = 0x00;
}

//SPI initialize
//
void spi_init(void)
{
SPCR = 0x53;
//setup SPI
SPSR = 0x00;
//setup SPI
}

//call this routine to initialize all peripherals
void init_devices(void)
{
//stop errant interrupts until set up
CLI();
//disable all interrupts
XDIV = 0x00;
//xtal divider
XMCRA = 0x00;
//external memory
port_init();
spi_init();

MCUCR = 0x00;
EICRA = 0x00;
//extended ext ints
EICRB = 0x00;
//extended ext ints
EIMSK = 0x00;
TIMSK = 0x00;
//timer interrupt sources
ETIMSK = 0x00;
//extended timer interrupt sources
SEI();
//re-enable interrupts
//all peripherals are now initialized
}

unsigned char shift_data_io(unsigned char c) {

SPDR = c;
while(!(SPSR & (1<<SPIF))) ;
return(SPDR);
}
//

void init_LS7366(void) {

LS7366_SS_L_H
// Initialize SS

LS7366_SS_H_L
// Set MDR0 X4 Count Mode
shift_data_io(SELECT_MDR0 | WR_REG);
shift_data_io(X4_QUAD | FREE_RUN | DISABLE_INDEX | SYNCHRONOUS_INDEX | FILTER_CDF_1 );
LS7366_SS_L_H

LS7366_SS_H_L
// Set MDR1 4 Bytes Counter Mode
shift_data_io(SELECT_MDR1 | WR_REG);
shift_data_io(FOUR_BYTE_COUNT_MODE | ENABLE_COUNTING);
LS7366_SS_L_H

LS7366_SS_H_L
// Clear(0) CNTR Register
shift_data_io(SELECT_CNTR | CLR_REG);
LS7366_SS_L_H

}

//////////////////////////////////////////////////////////////////////////////////////////////////////////////
void main(void) {

init_devices();
init_LS7366();

while (1) {
LS7366_SS_H_L
// Transfer CNTR to OTR in "parallel"
shift_data_io(SELECT_OTR | LOAD_REG);
LS7366_SS_L_H

LS7366_SS_H_L
// Read 4 Bytes OTR Register
shift_data_io(SELECT_OTR | RD_REG);
//
PORTF = shift_data_io(0x00);
// B31 - B24 MSB
PORTA = shift_data_io(0x00);
// B23 - B16
PORTC = shift_data_io(0x00);
// B15 - B08
PORTD = shift_data_io(0x00);
// B07 - B00 LSB
LS7366_SS_L_H

}
}

/////////////////////////////// End of FILE //////////////////////////////////////////////////////////////////


LS7566R-TS - 24Bit x 4-Axis Quadrature Clock Counter
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* 24 Bit 4 Axis Quadrature Counter
* x1, x2, x4 Quadrature ¸ðµå

LS7566R-TS: TSSOP

LS7766 - 32Bit Quadrature Counter (8Bit / 16Bit Bus, Single / Dual Axis)

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LS7766DH -> 2 Ãà 16/8 ºñÆ® µ¥ÀÌÅÍ ¹ö½º
LS7766DO -> 2 Ãà 8 ºñÆ® µ¥ÀÌÅÍ ¹ö½º
LS7766SH -> 1 Ãà 16/8 ºñÆ® µ¥ÀÌÅÍ ¹ö½º
LS7766SO -> 1Ãà 8 ºñÆ® µ¥ÀÌÅÍ ¹ö½º

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* Quadrature 9.6MHz Ä«¿îÆ® (5V, 40MHz)

LS7766DH-TS: TSSOP
LS7766DO: DIP
LS7766DO-S: SOIC
LS7766DO-TS: TSSOP
LS7766SO: DIP
LS7766SO-S: SOIC
LS7766SO-TS: TSSOP
LS7766SH-TS: TSSOP

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SOIC Outline Drawing
TSSOP Outline Drawing

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LSI PART NUMBERS  Data Sheet °¡°Ý (VAT º°µµ)
LS7183 (Dip)
LS7183-S (SOIC)
A/B Quad to Up/Down 4,100 ¿ø
LS7184 (Dip)
LS7184-S (SOIC)
A/B to CLK/Direction 4,100 ¿ø
LS7166 (20Pin Dip)
LS7166-S (20Pin SOIC)
LS7166-TS24 (24Pin TSSOP)
24 Bit Quad. Counter
8 Bit Data Bus
15,000 ¿ø
LS7266R1-D (Dip)
LS7266R1-SD (Skinny Dip)
2 x 24 Bit Quad Counter
8 Bit Data Bus
19,000 ¿ø
LS7266R1-S (SOIC)
LS7266R1-TS (TSSOP)
2 x 24 Bit Quad Counter
8 Bit Data Bus
18,000 ¿ø
LS7366R (Dip)
LS7366R-S (SOIC)
LS7366R-TS (TSSOP)
32 Bit Quad. Counter
SPI Bus
5,300  ¿ø
LS7566R-TS (TSSOP) 4 x 24 Bit Quad Counter 19,000 ¿ø
LS7766SO (Dip)
LS7766SO-S (SOIC)
LS7766SO-TS (TSSOP)
Quad. Counter
8 Bit Data Bus
13,500 ¿ø
LS7766SH-TS (TSSOP) 16 Bit Data Bus 14,500 ¿ø
LS7766DO (Dip)
LS7766DO-S (SOIC)
LS7766DO-TS (TSSOP)
Quad. Counter
8 Bit Data Bus
15,000 ¿ø
LS7766DH-TS (TSSOP) 16 Bit Data Bus 16,000 ¿ø
LS7290 (Dip) Stepper Motor Cntr 3,800 ¿ø
LS8297 (Dip)
LS8297-S (SOIC)
LS8297-TS (TSSOP)
Stepper Motor Cntr 5,200 ¿ø
LS8297CT (Dip)
LS8297CT-S (SOIC)
LS8297CT-TS (TSSOP)
Stepper Motor Cntr 5,900 ¿ø
LS8397 (Dip) Stepper Motor Cntr 6,700 ¿ø
LS8397-S (SOIC)
LS8397-TS (TSSOP)
Stepper Motor Cntr 6,500 ¿ø

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